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64- position otp digital potentiometer ad5171 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2008 analog devices, inc. all rights reserved. features 64 position one-time programmable (otp) set-and-forget resistance settinglow cost alternative over eemem unlimited adjustments prior to otp activation 5 k, 10 k, 50 k, 100 k end-to-end resistance low temperature coefficient: 5 ppm/c in potentiometer mode low temperature coefficient: 35 ppm/c in rheostat mode compact standard 8-lead sot-23 package low power: i dd = 10 a maximum fast settling time: t s = 5 s typical in power-up i 2 c-compatible digital interface computer software replaces microcontroller in factory programming applications full read/write of wiper register extra i 2 c device address pin low operating voltage: 2.7 v to 5.5 v otp validation check function automotive temperature range: ?40c to +125c applications system calibrations electronics level settings mechanical trimmers and potentiometer replacements automotive electronics adjustments gain control and offset adjustments transducer circuit adjustments programmable filters up to 1.5 mhz bw 1 general description the ad5171 is a 64-position, one-time programmable (otp) digital potentiometer 2 that uses fuse link technology to achieve the memory retention of the resistance setting function. otp is a cost-effective alternative over the eemem approach for users who do not need to reprogram new memory settings in the digital potentiometer. this device performs the same electronic adjustment function as most mechanical trimmers and variable resistors. the ad5171 is programmed using a 2-wire, i 2 c?- compatible digital control. it allows unlimited adjustments before permanently setting the resistance value. during the otp activation, a permanent fuse blown command is sent after the final value is determined, freezing the wiper position at a given setting (analogous to placing epoxy on a mechanical trimmer). functional block diagram gnd a w b v dd ad0 sda scl ad5171 03437-001 wiper register i 2 c interface and control logic fuse link figure 1. w 1 v dd 2 gnd 3 scl 4 a 8 b 7 ad0 6 sda 5 ad5171 top view (not to scale) 03437-002 figure 2. pin configuration when this permanent setting is achieved, the value does not change regardless of supply variations or environmental stresses under normal operating conditions. to verify the success of permanent programming, analog devices, inc., patterned the otp validation such that the fuse status can be discerned from two validation bits in read mode. for applications that program the ad5171 in factories, analog devices offers device programming software that operates across windows? 95 to xp platforms, including windows nt. this software application effectively replaces the need for external i 2 c controllers or host processors and, therefore, significantly reduces the development time of the users. an ad5171 evaluation kit includes the software, connector, and cable that can be converted for factory programming applications. the ad5171 is available in a compact 8-lead sot-23 package. all parts are guaranteed to operate over the automotive temper- ature range of ?40c to +125c. besides its unique otp feature, the ad5171 lends itself well to other general-purpose digital potentiometer applications due to its temperature performance, small form factor, and low cost. 1 applies to 5 k parts only. 2 the terms digital potentiometer and rdac are used interchangeably.
ad5171 rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics: 5 k, 10 k, 50 k, and 100 k .. 3 ? timing characteristics: 5 k, 10 k, 50 k, and 100 k ...... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 12 ? one-time programming (otp) .............................................. 12 ? variable resistance and voltage for rheostat mode ............. 13 ? variable resistance and voltage for potentiometer mode .... 13 ? power supply considerations ................................................... 14 ? esd protection ........................................................................... 14 ? terminal voltage operating range .......................................... 15 ? power-up/power-down sequences ......................................... 15 ? controlling the ad5171 ................................................................ 16 ? software programming ............................................................. 16 ? device programming ................................................................. 16 ? i 2 c controller programming .................................................... 17 ? i 2 c-compatible 2-wire serial bus ........................................... 17 ? controlling two devices on one bus ..................................... 18 ? applications information .............................................................. 19 ? dac .............................................................................................. 19 ? gain control compensation .................................................... 19 ? programmable voltage source with boosted output ........... 19 ? level shifting for different voltage operation ...................... 19 ? resistance scaling ...................................................................... 19 ? resolution enhancement .......................................................... 20 ? rdac circuit simulation model ............................................. 20 ? evaluation board ............................................................................ 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 7 /08rev. c to rev. d changes to power supplies parameter in table 1.........................3 updated fuse blow condition to 400 ms throughout ...............5 1/08rev. b to rev. c updated format .................................................................. universal deleted note 1; renumbered sequentially ................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 3 ............................................................................ 6 changes to table 4 ............................................................................ 7 changes to figure 13 to figure 16 .................................................. 9 changes to figure 17 and figure 18 ............................................. 10 inserted figure 24 ........................................................................... 11 changes to one-time programming (otp) section and power supply considerations section ..................................................... 12 deleted figure 25 and figure 26 ................................................... 13 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 1/05rev. a to rev. b change to features ............................................................................ 1 changes to electrical characteristics ............................................. 3 change to table 3 .............................................................................. 6 changes to power supply considerations section .................... 13 changes to level shifting for different voltage operation section .............................................................................................. 19 added note to ordering guide .................................................... 22 11/04rev. 0 to rev. a changes to specifications ................................................................. 3 changes to table 3 ............................................................................. 7 changes to one-time programming section ............................ 11 changes to power supply consideration section ...................... 11 changes to figure 26 and figure 27............................................. 12 1/04revision 0: initial version
ad5171 rev. d | page 3 of 24 specifications electrical characteristics: 5 k, 10 k, 50 k, and 100 k v dd = 3 v to 5 v 10%, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect, r ab = 10 k, 50 k, and 100 k ?0.5 0.1 +0.5 lsb r wb , v a = no connect, r ab = 5 k ?1 0.25 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect, r ab = 10 k, 50 k, and 100 k ?1.5 0.35 +1.5 lsb r wb , v a = no connect, r ab = 5 k ?1.5 0.5 +1.5 lsb nominal resistor tolerance 3 ?r ab /r ab ?30 +30 % resistance temperature coefficient (?r ab /r ab )/?t 35 ppm/c wiper resistance r w v dd = 5 v 60 115 dc characteristics potentiometer divider mode (specifications apply to all rdacs) resolution n 6 bits differential nonlinearity 4 dnl ?0.5 0.1 +0.5 lsb integral nonlinearity 4 inl ?1 0.2 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x20 5 ppm/c full-scale error v wfse code = 0x3f, r ab = 10 k, 50 k, and 100 k ?1 ?0.5 0 lsb full-scale error v wfse code = 0x3f, r ab = 5 k ?1.5 0 lsb zero-scale error v wzse code = 0x00, r ab =10 k, 50 k, and 100 k 0 0.5 1 lsb code = 0x00, r ab = 5 k 0 2 lsb resistor terminals voltage range 5 v a, v b, v w with respect to gnd v dd v capacitance a, b 6 c a, c b f = 1 mhz, measured to gnd, code = 0x20 25 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x20 55 pf common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs input logic high (sda and scl) 7 v ih 0.7 v dd v dd + 0.5 v input logic low (sda and scl) 7 v il ?0.5 +0.3 v dd v input logic high (ad0) v ih v dd = 3 v 3.0 v dd v input logic low (ad0) v il v dd = 3 v 0 1.0 v input current i il v in = 0 v or 5 v 1 a input capacitance 8 c il 3 pf digital outputs output logic low (sda) v ol i ol = 6 ma 0.4 v three-state leakage current (sda) i oz v in = 0 v or 5 v 1 a output capacitance 8 c oz 3 pf power supplies power supply range v dd 2.7 5.5 v otp power supply 7 , 9 v dd_otp t a = 25c 4.75 5 5.25 v supply current i dd v ih = 5 v or v il = 0 v 4 10 a otp supply current 7 , 10 , 11 i dd_otp v dd_otp = 5 v, t a = 25c 100 ma power dissipation 12 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.02 0.055 mw power supply sensitivity pssr ?0.025 +0.001 +0.025 %/%
ad5171 rev. d | page 4 of 24 parameter symbol conditions min typ 1 max unit dynamic characteristics 8 , 13 , 14 C3 db bandwidth bw_5k r ab = 5 k, code = 0x20 1500 khz bw_10k r ab = 10 k, code = 0x20 600 khz bw_50k r ab = 50 k, code = 0x20 110 khz bw_100k r ab = 100 k, code = 0x20 60 khz total harmonic distortion thd v a = 1 v rms, r ab = 10 k, v b = 0 v dc, f = 1 khz 0.05 % adjustment settling time t s1 v a = 5 v 1 lsb error band, v b = 0 v, measured at v w 5 s power-up settling time after fuses blown t s2 v a = 5 v 1 lsb error band, v b = 0 v, measured at v w 5 s resistor noise voltage e n_wb r ab = 5 k, f = 1 khz, code = 0x20 8 nv/hz r ab = 10 k, f = 1 khz, code = 0x20 12 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. 6 guaranteed by design; not subject to production test. 7 the minimum voltage re quirement on the v ih is 0.7 v v dd . for example, v ih minimum = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull- up resistors. 8 guaranteed by design; not subject to production test. 9 different from operating power supply; power supply for otp is used one time only. 10 different from operating current; su pply current for otp lasts approximat ely 400 ms for one -time need only. 11 see figure 24 for the energy plot during the otp program. 12 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 13 bandwidth, noise, and settling time depend on the terminal resistance value chosen. the lowest r value results in the fastest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 14 all dynamic characteristics use v dd = 5 v.
ad5171 rev. d | page 5 of 24 timing characteristics: 5 k, 10 k, 50 k, and 100 k v dd = 3 v to 5 v 10%, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit interface timing characteristics (apply to all parts 2 , 3 ) scl clock frequency f scl 400 khz t buf bus free time between start and stop t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 0.1 s t f fall time of both sda and scl signals t 8 0.3 s t r rise time of both sda and scl signals t 9 0.3 s t su;sto setup time for stop condition t 10 0.6 s otp program time t 11 400 ms 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 guaranteed by design; not subject to production test. 3 all dynamic characteristics use v dd = 5 v. scl s da t 1 t 2 t 3 t 8 t 8 t 9 t 4 t 5 t 9 t 7 t 6 t 10 p ps 03437-024 figure 3. interface timing diagram
ad5171 rev. d | page 6 of 24 absolute maximum ratings table 3. parameter rating v dd to gnd ?0.3 v to +7 v v a , v b , and v w to gnd gnd to v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k, a open) 1 5 ma i wa continuous (r wa 1 k, b open) 1 5 ma digital inputs and output voltage to gnd 0 v to v dd operating temperature range ?40c to +125c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec thermal resistance ja 2 230c/w 1 maximum terminal current is boun ded by the maximum applied voltage across any two of the a, b, and w terminals at a given resistance; the maximum current handling of the sw itches, and the maximum power dissipation of the package. v dd = 5 v. 2 package power dissipation = (t j max C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5171 rev. d | page 7 of 24 pin configuration and fu nction descriptions w 1 v dd 2 gnd 3 scl 4 a 8 b 7 ad0 6 sda 5 ad5171 top view (not to scale) 03437-003 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 w wiper terminal w. gnd v w v dd . 2 v dd positive power supply. specified for operation from 2.7 v to 5.5 v. for otp programming, v dd needs to be within the 4.75 v and 5.25 v range and capable of driving 100 ma. 3 gnd common ground. 4 scl serial clock input. requires a pull-up resistor. if it is driven direct from a logic controller without the pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 5 sda serial data input/output. requires a pull-up resistor. if it is driven direct from a logic controller without a pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 6 ad0 i 2 c device address bit. allows a maximum of two ad5171s to be addressed. 7 b resistor terminal b. gnd v b v dd . 8 a resistor terminal a. gnd v a v dd .
ad5171 rev. d | page 8 of 24 typical performance characteristics ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 rheost a t mode inl (lsb) 32 24 816 0 40485664 code (decimal) 03437-004 ?40c +25c +125c v dd = 5v figure 5. r-inl vs. code vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 rheost a t mode dnl (lsb) 3224 816 0 40485664 code (decimal) 03437-005 ?40c +25c +125c v dd = 5v figure 6. r-dnl vs. code vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 potentiometer mode inl (lsb) 3224 816 0 40485664 code (decimal) 03437-006 ?40c +25c +125c v dd = 5v figure 7. inl vs. code vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 potentiometer mode dnl (lsb) 3224 816 0 40485664 code (decimal) 03437-007 ?40c +25c +125c v dd = 5v figure 8. dnl vs. code vs. temperature ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 fse (lsb) ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 03437-008 v dd = 5v v dd = 3v figure 9. full-scale error (fse) vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 zse (lsb) ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 03437-009 v dd = 5v v dd = 3v figure 10. zero-scale error (zse) vs. temperature
ad5171 rev. d | page 9 of 24 i dd supply current (a) 0.1 1 10 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 03437-010 v dd = 5v v dd = 3v figure 11. i dd supply current vs. temperature ?40 ?20 20 100 140 180 60 0 80 120 160 40 rheost a t mode tempco (ppm/c) 3224 816 0 40485664 code (decimal) 03437-011 figure 12. rheostat mode tempco (?r ab /r ab )/?t vs. code ?5 0 5 10 15 20 25 potentiometer mode tempco (ppm/c) 3224 816 0 40485664 code (decimal) 03437-012 figure 13. potentiometer mode tempco (?v w /v w )/?t vs. code 100 1m 1k 10k 100k 10m frequency (hz) 0 6 ?6 ?12 ?18 ?24 ?30 ?36 ?54 ?42 ?48 gain (db) 0x02 0x01 0x00 0x04 0x08 0x10 0x20 03437-013 figure 14. gain vs. frequency vs. code, r ab = 5 k 100 1m 1k 10k 100k frequency (hz) 0 6 ?6 ?12 ?18 ?24 ?30 ?36 ?54 ?42 ?48 gain (db) 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 03437-014 figure 15. gain vs. frequency vs. code, r ab = 10 k 100 1m 1k 10k 100k frequency (hz) 0 6 ?6 ?12 ?18 ?24 ?30 ?36 ?54 ?42 ?48 gain (db) 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 03437-015 figure 16. gain vs. frequency vs. code, r ab = 50
ad5171 rev. d | page 10 of 24 frequency (hz) 100 1k 0 ?6 6 ?12 ?18 ?24 ?30 ?36 ?54 ?42 ?48 gain (db) 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 1m 10k 100k 03437-016 figure 17. gain vs. frequency vs. code, r ab = 100 k frequency (hz) 80 40 100 1m 1k 10k 100k power supply rejection r a tio (db) 60 20 0 t a = 25c code = 0x20 v a = 2.5v, v b = 0v v dd = 5v dc 1.0v p-p ac v dd = 3v dc 0.6v p-p ac 03437-017 figure 18. power supply reje ction ratio vs. frequency 03437-018 v dd = 5.5v v a = 5.5v v b = gnd f clk = 100khz 10mv 500ns v w = 10mv/div scl = 5v/div 5v figure 19. digital feedthrough vs. time 03437-019 v dd = 5.5v v a = 5.5v v b = gnd f clk = 400khz data 0x00 0x3f 5s 5v 5v v w = 5v/div scl = 5v/div figure 20. settling time 03437-020 v dd = 5.5v v a = 5.5v v b = gnd f clk = 100khz data 0x20 0x1f 50mv 200ns 5v v w = 50mv/div scl = 5v/div figure 21. midscale glitch energy 03437-021 5s 5v 1v otp programmed at ms v dd = 5.5v v a = 5.5v r ab = 10k ? v w = 1v/div v dd = 5v/div figure 22. power-up settling time after fuses blown
ad5171 rev. d | page 11 of 24 theoretic a l i wb_max (ma) 0.01 1 0.1 10 3224 816 0 40485664 code (decimal) 03437-0-022 v a = v b = open t a = 25c r ab = 100k ? r ab = 50k ? r ab = 10k ? r ab = 5k ? 03437-023 ch1 20.0ma ? m 200ns a ch1 32.4ma 1 t 588.000ns ch1 max 103ma ch1 min ?1.98ma figure 24. otp program energy plot for single fuse figure 23. theoretical i wb _ max vs. code
ad5171 rev. d | page 12 of 24 theory of operation 03437-025 sda scl a w b comparator mux decoder fuses en fuse reg. dac reg. i 2 c interface one-time program/test control block figure 25. detailed fu nctional block diagram the ad5171 allows unlimited 6-bit adjustments, except for the one-time programmable, set-and-forget resistance setting. otp technology is a proven, cost-effective alternative over eemem in one-time memory programming applications. the ad5171 employs fuse link technology to achieve the memory retention of the resistance setting function. it has six data fuses that control the address decoder for programming the rdac, one user mode test fuse for checking setup error, and one programming lock fuse for disabling any further programming once the data fuses are blown. one-time programming (otp) prior to otp activation, the ad5171 presets to midscale during initial power-on. after the wiper is set at the desired position, the resistance can be permanently set by programming the t bit high along with the proper coding (see table 8 and table 9 ) and one-time v dd_otp . the fuse link technology of the ad517x family of digital potentiometers requires v dd_otp between 4.75 v and 5.25 v to blow the fuses to achieve a given nonvolatile setting. on the other hand, v dd can be 2.7 v to 5.5 v during operation. as a result, a system supply that is lower than 4.75 v requires external supply for otp. in addition, the user is only allowed one attempt in blowing the fuses. if the user fails to blow the fuses at the first attempt, the fuse structures may change so that they may never be blown regardless of the energy applied at subsequent events. for details, see the power supply considerations section. the device control circuit has two validation bits, e1 and e0, that can be read back to check the programming status (see table 5 ). users should always read back the validation bits to ensure that the fuses are properly blown. after the fuses are blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. table 5. validation status e1 e0 status 0 0 ready for programming. 0 1 test fuse not blown successfully. for factory setup checking purpose only. users should not see these combinations. 1 0 fatal error. some fuses are not blown. do not retry. discard the unit. 1 1 successful. no further programming is possible. this section discusses the fuse operation in detail. when the otp t bit is set, the internal clock is enabled. the program then attempts to blow a test fuse. the operation stops if the test fuse is not properly blown. the validation bits, e1 and e0, show 01. this status is intended for factory setup checking purposes only; users should not see this status. if the test fuse is properly blown, the data fuses can be programmed. the six data fuses are programmed in six clock cycles. the output of the fuses is compared with the code stored in the rdac register. if they do not match, e1 and e0 of 10 are issued as fatal errors and the operation stops. users should never try blowing the fuses more than once because the fuse structure may have changed prohibiting further programming. as a result, the unit must be discarded. this error status can also occur if the otp supply voltage goes above or drops below the v dd_otp requirement, the otp supply current is limited, or both the voltage and current ramp times are slow. if the output and stored code match, the programming lock fuse is blown so that no further programming is possible. in the meantime, e1 and e0 issue 11, indicating the lock fuse is properly blown. all the fuse latches are enabled at power-on; therefore, from this point on, the output corresponds to the stored setting. figure 25 shows a detailed functional block diagram.
ad5171 rev. d | page 13 of 24 variable resistance and voltage for rheostat mode if only the w-to-b or w-to-a terminals are used as variable resistors, the unused terminal can be opened or shorted with terminal w. this operation is called rheostat mode (see figure 26 ). a w b a w b a w b 0 3437-050 figure 26. rheostat mode configuration the nominal resistance (r ab ) of the rdac has 64 contact points accessed by the wiper terminal, plus terminal b contact if r wb is considered. the 6-bit data in the rdac latch is decoded to select one of the 64 settings. assuming that a 10 k part is used, the first connection of the wiper starts at terminal b for data 0x00. such a connection yields a minimum of 60 resistance between te r m i n a l w a n d te r m i n a l b du e to t h e 6 0 w ip e r c ont a c t resistance. the second connection is the first tap point, which corresponds to 219 ( r wb = 1 r ab /63 + r w ) for data 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,060 (63 r ab /63 + r w ). figure 27 shows a simplified diagram of the equivalent rdac circuit. the general equation determining r wb is w ab wb rr d dr += 63 )( (1) where: d is the decimal equivalent of the 6-bit binary code. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on-resistance of the internal switch. table 6. r wb vs. codes: r ab = 10 k; terminal a open d (dec) r wb () output state 63 10060 full-scale (r ab + r w ) 32 5139 midscale 1 219 1 lsb 0 60 zero-scale (wiper contact resistance) because a finite wiper resistance of 60 is present in the zero- scale condition, care should be taken to limit the current flow b e t we e n ter m in a l w and ter m i na l b i n t his st ate to a m ax i mu m pulse current 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper (terminal w) and terminal a also produces a complementary resistance, r wa . when these terminals are used, terminal b can be opened or shorted to terminal w. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr + ? = 63 63 )( (2) table 7. r wa vs. codes: r ab = 10 k; terminal b open d (dec) r wa () output state 63 60 full-scale 32 4980 midscale 1 9901 1 lsb 0 10060 zero-scale the typical distribution of the resistance tolerance from device to device is process-lot dependent; it is possible to have 30% tolerance. r s r s r s a w b d5 d4 d3 d2 d1 d0 rdac latch and decoder 03437-026 figure 27. ad5171 equivalent rdac circuit variable resistance and voltage for potentiometer mode if all three terminals are used, the operation is called the potentiometer mode. the most common configuration is the voltage divider operation (see figure 28 ). a w b v i v o 0 3437-051 figure 28. potentiometer mode configuration
ad5171 rev. d | page 14 of 24 ignoring the effect of the wiper resistance, the transfer function is simply a w v d dv 63 )( = (3) a more accurate calculation, which includes the wiper resistance effect, yields a w ab w ab w v rr rr d dv 2 63 )( + + = (4) unlike in rheostat mode where the absolute tolerance is high, potentiometer mode yields an almost ratiometric function of d/63 with a relatively small error contributed by the r w terms; thus, the tolerance effect is almost cancelled. although the thin film step resistor (r s ) and cmos switches resistance (r w ) have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/c, except at low value codes where r w dominates. potentiometer mode includes other operations such as op amp input, feedback resistor networks, and voltage scaling applications. terminal a, terminal w, and terminal b can, in fact, be input or output terminals provided that |v ab |, |v wa |, and |v wb | do not exceed v dd to gnd. power supply considerations to minimize the package pin count, both the otp and normal operating voltage supplies share the same v dd terminal of the ad5171. the ad5171 employs fuse link technology that requires 4.75 v to 5.25 v for blowing the internal fuses to achieve a given setting, but normal v dd can be anywhere between 2.7 v and 5.5 v after the fuse programming process. as a result, dual voltage supplies and isolation are needed if system v dd is lower than the required v dd_otp . the fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 4.75 v to 5.25 v and able to provide a 100 ma current for 400 ms for successful one-time programming. once fuse programming is complete, the v dd_otp supply must be removed to allow normal operation at 2.7 v to 5.5 v; the device then consumes current in the a range. 03437-052 v dd 2 .7 v 5v p1 r1 10k? p2 apply for o t p only ad5171 c2 0.1f c1 10f p1 = p2 = fdv302p, nds0610 figure 29. 5 v otp supply isolated from the 2.7 v normal operating supply; the v dd_otp supply must be removed once otp is complete. when operating at 2.7 v, use of the bidirectional low threshold p-ch mosfets is recommended for the isolation of the supply. as shown in figure 29 , this assumes that the 2.7 v system voltage is applied first, and the p1 and p2 gates are pulled to ground, thus turning on p1 and, subsequently, p2. as a result, v dd of the ad5171 approaches 2.7 v. when the ad5171 setting is found, the factory tester applies the v dd_otp to both the v dd and the mosfets gates, thus turning off p1 and p2. the otp command should be executed at this time to program the ad5171 while the 2.7 v source is protected. once the fuse programming is complete, the tester withdraws the v dd_otp and the setting of the ad5171 is permanently fixed. the ad5171 achieves the otp function through blowing internal fuses. users should always apply the 4.75 v to 5.25 v one-time program voltage requirement at the first fuse programming attempt. failure to comply with this requirement may lead to a change in the fuse structures, rendering programming inoperable. care should be taken when scl and sda are driven from a low voltage logic controller. users must ensure that the logic high level is between 0.7 v v dd and v dd . refer to the level shifting for different voltage operation section. poor pcb layout introduces parasitics that may affect the fuse programming. therefore, it is recommended that a 10 f tantalum capacitor be added in parallel with a 1 nf ceramic capacitor as close as possible to the v dd pin. the type and value chosen for both capacitors are important. this combination of capacitor values provides both a fast response and larger supply current handling with minimum supply droop during transients. as a result, these capacitors increase the otp programming success by not inhibiting the proper energy needed to blow the internal fuses. additionally, c1 minimizes transient disturbance and low frequency ripple, while c2 reduces high frequency noise during normal operation. esd protection digital inputs sda and scl are protected with a series input resistor and parallel zener esd structures (see figure 30 ). logic 340 ? gnd 03437-027 figure 30. esd protection of digital pins
ad5171 rev. d | page 15 of 24 terminal voltage operating range power-up/power-down sequences there are also esd protection diodes between v dd and the rdac terminals; therefore, the v dd of the ad5171 defines their voltage boundary conditions (see figure 31 ). supply signals present on terminal a, terminal b, and terminal w that exceed v dd are clamped by the internal forward-biased diodes and should be avoided. similarly, because of the esd protection diodes, it is important to power v dd first before applying any voltages to terminal a, te r m i n a l b, a nd te r m i n a l w. o t he r w i s e, t he d i o d e i s f or w ard - biased such that v dd is powered unintentionally and can affect the remainder of the users circuits. the ideal power-up sequence is the following order: gnd, v dd , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd . similarly, v dd should be powered down last. gnd a w b v dd 03437-029 figure 31. maximum terminal voltages set by v dd
ad5171 rev. d | page 16 of 24 controlling the ad5171 there are two ways of controlling the ad5171. users can either program the devices with computer software or employ external i 2 c controllers. software programming due to the advantage of the one-time programmable feature, users may consider programming the device in the factory before shipping it to the end users. analog devices offers device programming software that can be implemented in the factory on pcs running windows 95 to windows xp platforms. as a result, external controllers are not required, which significantly reduces development time. the program is an executable file that does not require the user to know any programming languages or programming skills. it is easy to set up and use. figure 32 shows the software interface. the software can be downloaded from the ad5171 product page. 03437-032 figure 32. software interface write the ad5171 starts at midscale after power-up prior to the otp programming. to increment or decrement the resistance, move the scrollbar on the left. to write any specific values, use the bit pattern control in the upper screen and click run . the format of writing data to the device is shown in table 8 . once the desired setting is found, click program permanent to blow the internal fuse links for permanent setting. the user can also set the programming bit pattern in the upper screen and click run to achieve the same result. read to read the validation bits and data from the device, click read . the user may also set the bit pattern in the upper screen and click run . the format of reading data out from the device is shown in table 9 . device programming to apply the device programming software in the factory, users need to modify a parallel port cable and configure pin 2, pin 3, pin 15, and pin 25 for sda_write, scl, sda_read, and dgnd, respectively, for the control signals (see figure 33 ). in addition, lay out the pcb of the ad5171 with scl and sda pads, as shown in figure 34 , such that pogo pins can be inserted for the factory programming. 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100? r2 100 ? r1 100? sda read write 0 3437-033 figure 33. parallel port connection: pin 2 = sda_write, pin 3 = scl, pin 15 = sda_read, and pin 25 = dgnd w v dd gnd scl a b ad0 sda 04104-034 figure 34. recommended ad5171 pcb layout table 8. sda write mode bit format s 0 1 0 1 1 0 ad0 0 a t x x x x x x x a x x d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 9. sda read mode bit format s 0 1 0 1 1 0 ad0 1 a e1 e0 d5 d4 d3 d2 d1 d0 a p slave address byte data byte
ad5171 rev. d | page 17 of 24 table 10. sda bits definitions and descriptions bit description s start condition. p stop condition. a acknowledge. ad0 i 2 c device address bit. allows a maximum of two ad5171s to be addressed. x dont care. t otp programming bit. logic 1 programs the wiper position permanently. d5, d4, d3, d2, d1, d0 data bits. e1, e0 otp validation bits: 0, 0 = ready to program. 0, 1 = test fuse not blown successfully. for factory se tup checking purpose only. users should not see these combinations. 1, 0 = fatal error. do not retry. discard the unit. 1, 1 = programmed successfully. no further adjustments are possible. i 2 c controller programming write bit patterns sda scl 0 1 1 0 11 0 ad0 r/w 0 x x x x x x x x xd5 d4 d3 d2 d1 d0 91 91 9 stop by master frame 1 data byte frame 2 instruction byte frame 1 slave address byte s tart by master ack. by ad5171 ack. by ad5171 ack. by ad5171 03437-035 figure 35. writing to the rdac register sda scl 0 1 1 0 11 0 ad0 r/w 1x x x x x x x x x d5d4d3d2d1 d0 91 91 9 stop by master frame 1 data byte frame 2 instruction byte frame 1 slave address byte start by master ack. by ad5171 ack. by ad5171 ack. by ad5171 03437-036 figure 36. activating one-time programming read bit pattern sda scl 0 1 1 0 11 0 ad0 e1 e0 d5 d4 d3 d2 d1 d0 91 9 r/w stop by master frame 2 rdac register frame 1 slave address byte start by master no ack. by master ack. by ad5171 03437-037 figure 37. reading data from rdac register i 2 c-compatible 2-wire serial bus for users who prefer to use external controllers, the ad5171 can be controlled via an i 2 c-compatible serial bus; the part is connected to this bus as a slave device. the following section describes how the 2-wire i 2 c serial bus protocol operates (see figure 35 , figure 36 , and figure 37 ). the master initiates data transfer by establishing a start condition, which is when sda goes from high to low while scl is high (see figure 35 and figure 36 ). the following byte is the slave address byte, which consists of the 6 msbs as a slave address defined as 010110. the next bit is ad0, which is an i 2 c device address bit. depending on the states of their ad0 bits, two ad5171s can be addressed on the same bus (see figure 38 ). the last lsb is the r/ w bit, which determines whether data is read from, or written to, the slave device. the slave address corresponding to the transmitted address bit responds by pulling the sda line low during the 9 th clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. the write operation contains one instruction byte more than the read operation. the instruction byte in the write mode follows the slave address byte. the msb of the instruction byte labeled t is the one-time programming bit. after acknowledging
ad5171 rev. d | page 18 of 24 the instruction byte, the last byte in the write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 35 ). in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (note the slight difference from the write mode; there are eight data bits followed by a no acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 37 ). when all data bits are read or written, a stop condition is established by the master. a stop condition is defined as a low- to-high transition on the sda line while scl is high. in the write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 35 and figure 36 ). in the read mode, the master issues a no acknowledge for the 9 th clock pulse, that is, the sda line remains high. the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 37 ). a repeated write function gives the user flexibility to update the rdac output a number of times, except after permanent programming, addressing, and instructing the part only once. during the write cycle, each data byte updates the rdac output. for example, after the rdac has acknowledged its slave address and instruction bytes, the rdac output updates after these two bytes. if another byte is written to the rdac while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. if different instructions are needed, the write mode has to be started with a new slave address, instruction, and data bytes. similarly, a repeated read function of the rdac is also allowed. controlling two devices on one bus figure 38 shows two ad5171 devices on the same serial bus. each has a different slave address because the state of each ad0 pin is different, which allows each device to be independently operated. the master device output bus line drivers are open- drain pull-downs in a fully i 2 c-compatible interface. master sda scl ad0 ad5171 sda scl ad0 ad5171 sda scl 5 v rp rp 5v 03437-038 figure 38. two ad5171 devices on one bus
ad5171 rev. d | page 19 of 24 applications information dac it is common to buffer the output of the digital potentiometer as a dac unless the load is much larger than r wb . the buffer can impede conversion and deliver higher current, if needed. gnd v in v out 1 5 v 2 3 v o ad8601 5v a w b u1 ad1582 a1 ad5171 u2 03437-039 figure 39. programmable voltage reference (dac) gain control compensation the digital potentiometers are commonly used in gain controls or sensor transimpedance amplifier signal conditioning applications (see figure 40 ). to avoid gain peaking, or in worst- case oscillation due to step response, a compensation capacitor is needed. in general, c2 in the range of a few picofarads to a few tenths of a picofarad is adequate for the compensation. u1 c2 4.7pf a b w r2 100k? v o v i r1 47k ? 0 3437-040 figure 40. typical noninverting gain amplifier programmable voltage source with boosted output for applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 41 ). +v w signal c c r bias ld v in a b v out u1 a d5171 u3 2n7002 ad8601 u2 ?v i l 03437-041 figure 41. programmable booster voltage source in this circuit, the inverting input of the op amp forces the v out to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n?ch fet n 1 . n 1 power handling must be adequate to dissipate (v i ? v o ) i l power. this circuit can source a maximum of 100 ma with a 5 v supply. for precision applications, a voltage reference, such as the adr421 , adr03 , or adr370 , can be applied at terminal a of the digital potentiometer. level shifting for different voltage operation if the scl and sda signals come from a low voltage logic controller and are below the minimum v ih level (0.7 v v dd ), level shift the signals for read/write communications between the ad5171 and the controller. figure 42 shows one of the implementations. for example, when sda1 is at 2.5 v, m1 turns off, and sda2 becomes 5 v. when sda1 is at 0 v, m1 turns on, and sda2 approaches 0 v. as a result, proper level shifting is established. m1 and m2 should be low threshold n-ch power mosfets, such as fdv301n. 2.5v controller 2.7v?5.5v ad5171 rp rp rp rp v dd1 = 2.5 v v dd2 = 5 v g g s d m1 s d m2 sda1 scl1 sda2 scl2 03437-042 figure 42. level shifting for different voltage operation resistance scaling the ad5171 offers 5 k, 10 k, 50 k, and 100 k nominal resistances. for users who need to optimize the resolution with an arbitrary full range resistance, the following techniques can be used. by paralleling a discrete resistor, a proportionately lower vo lt age app e ar s at te r m i n a l a to te r m i n a l b, w h i c h i s a p p l i c a b l e only to the voltage divider mode (see figure 43 ). this translates into a finer degree of precision because the step size at terminal w is smaller. the voltage can be found as dd ab ab w v d r2rr3 r2r dv 64|| )||( ) ( (5) r1 r2 b a v dd r3 w 03437-043 figure 43. lowering the nominal resistance
ad5171 rev. d | page 20 of 24 for log taper adjustment, such as volume control, figure 44 shows another way of resistance scaling. in this circuit, the smaller the r2 with respect to r ab , the more it behaves like the pseudo log taper characteristic. the wiper voltage is simply i wb wa wb w v 2rrr 2rr dv + = || )||( )( (6) v i r1 b a r2 v o w 0 3437-044 figure 44. resistor scaling with log adjustment characteristics resolution enhancement the resolution can be doubled in the potentiometer mode of operation by using three digital potentiometers. borrowed from the analog devices patented rdac segmentation technique, users can configure three ad5171s to double the resolution (see figure 45 ). first, u3 must be parallel with a discrete resistor, r p , which is chosen to be equal to a step resistance (r p = r ab /64). adjusting u1 and u2 together forms the coarse 6-bit adjustment, and adjusting u3 alone forms the finer 6-bit adjustment. as a result, the effective resolution becomes 12-bit. u1 a1 b1 w1 u2 a2 b2 w3 w2 u3 a3 b3 r p coarse adjustment fine adjustment 03437-045 figure 45. doubling the resolution rdac circuit simulation model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the digital potentiometers. configured as a potentiometer divider, the C3 db bandwidth of the ad5171 (5 k resistor) measures 1.5 mhz at half scale. figure 14 to figure 17 provide the large signal bode plot characteristics of the four available resistor versions: 5 k, 10 k, 50 k, and 100 k. a parasitic simulation model is shown in figure 46 . listing 1 provides a macro model net list for the 10 k device. 55pf c a 25pf c b 25pf a b rdac 10k ? w c w 03437-046 figure 46. circuit simulation model for rdac = 10 k listing 1. macro model net list for rdac .param d=64, rdac=10e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/64)*rdac+60} cw w 0 55e-12 rwb w b {d/64*rdac+60} cb b 0 25e-12 * .ends dpot
ad5171 rev. d | page 21 of 24 evaluation board 8 7 6 5 4 3 2 1 j1 w v dd gnd scl a b ad0 sda out1 out1 +in1 v+ v? ?in2 +in2 out2 ?in1 jp8 jp7 jp4 jp6 c8 0.1f c9 10f v ee u3a cp4 cp2 jp5 jp3 c6 0.1f c7 10f 1 2 3 4 8 5 6 7 ?in1 cp3 cp1 v in 1 ad5170 ad5171/ad5273 agnd v ref adr03 2 3 5 4 c1 10f c2 0.1f r1 10k? r2 10k? scl sda c3 0.1f u1 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 u2 c4 0.1f u4 temp gnd v in trim v out c5 0.1f jp1 jp2 a w b cp6 cp7 u3b v dd v dd w v dd gnd scl a b ad0 sda v dd v dd v cc cp5 03437-047 figure 47. evaluation board schematic the ad5171 evaluation board comes with a dual op amp ad822 and a 2.5 v reference adr03 . users can configure many building block circuits with minimal components needed. figure 48 shows one of the examples. there is space available on the board where users can build additional circuits for further evaluations as shown in figure 49 . a b w v o a b w cp2 u2 jp1 jp2 jp4 jp3 jp7 4 u3a 1 out1 v+ v? ad822 2 3 11 03437-048 v ref v ref v dd figure 48. programmable voltage reference 03437-049 figure 49. evaluation board
ad5171 rev. d | page 22 of 24 outline dimensions 13 56 2 8 4 7 2.90 bsc 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc pin 1 indicator compliant to jedec standards mo-178-b a figure 50. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters ordering guide model 1 r ab (k) temperature range package description package option ordering quantity branding ad5171brj5-r2 5 ?40c to +125c 8-lead sot-23 rj-8 250 d12 ad5171brj5-rl7 5 ?40c to +125c 8-lead sot-23 rj-8 3000 d12 ad5171brjz5-r2 2 5 ?40c to +125c 8-lead sot-23 rj-8 250 d12# ad5171brjz5-r7 2 5 ?40c to +125c 8-lead sot-23 rj-8 3000 d12# ad5171brj10-r2 10 ?40c to +125c 8-lead sot-23 rj-8 250 d13 ad5171brj10-rl7 10 ?40c to +125c 8-lead sot-23 rj-8 3000 d13 ad5171brjz10-r2 2 10 ?40c to +125c 8-lead sot-23 rj-8 250 d13# ad5171brjz10-r7 2 10 ?40c to +125c 8-lead sot-23 rj-8 3000 d13# ad5171brj50-r2 50 ?40c to +125c 8-lead sot-23 rj-8 250 d14 ad5171brj50-rl7 50 ?40c to +125c 8-lead sot-23 rj-8 3000 d14 ad5171brjz50-r2 2 50 ?40c to +125c 8-lead sot-23 rj-8 250 d14# ad5171brjz50-r7 2 50 ?40c to +125c 8-lead sot-23 rj-8 3000 d14# ad5171brj100-r2 100 ?40c to +125c 8-lead sot-23 rj-8 250 d15 ad5171brj100-rl7 100 ?40c to +125c 8-lead sot-23 rj-8 3000 d15 ad5171brjz100-r2 2 100 ?40c to +125c 8-lead sot-23 rj-8 250 d15# AD5171BRJZ100-R7 2 100 ?40c to +125c 8-lead sot-23 rj-8 3000 d15# ad5171ev al 3 10 evaluation board 1 1 parts have a yww or #yww marking on the bottom of the package. y shows the year that the part was made, for example, y = 5 for 2005. ww shows the work week that the part was made. 2 z = rohs compliant part, # denotes rohs compliant part may be top or bottom marked. 3 the evaluation board is shipped with three pieces of 10 k parts. users should order extra samples or different resistance options if needed.
ad5171 rev. d | page 23 of 24 notes
ad5171 rev. d | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2004C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03437-0-7 /08(d)

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